LPC23xx.h

00001 /******************************************************************************
00002  *   LPC23xx.h:  Header file for NXP LPC23xx/24xx Family Microprocessors
00003  *   The header file is the super set of all hardware definition of the
00004  *   peripherals for the LPC23xx/24xx family microprocessor.
00005  *
00006  *   Copyright(C) 2006, NXP Semiconductor
00007  *   All rights reserved.
00008  *
00009  *   History
00010  *   2005.10.01  ver 1.00    Prelimnary version, first Release
00011  *
00012  ******************************************************************************/
00013 
00014 /* Modified by Martin Thomas */
00015 /* Modified by David Ackley - generic UART offsets */
00016 
00017 #ifndef __LPC23xx_H
00018 #define __LPC23xx_H
00019 
00020 /* Vectored Interrupt Controller (VIC) */
00021 #define VIC_BASE_ADDR   0xFFFFF000
00022 #define VICIRQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
00023 #define VICFIQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
00024 #define VICRawIntr     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
00025 #define VICIntSelect   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
00026 #define VICIntEnable   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
00027 #define VICIntEnClr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
00028 #define VICSoftInt     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
00029 #define VICSoftIntClr  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
00030 #define VICProtection  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
00031 #define VICSWPrioMask  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
00032 
00033 #define VICVectAddr0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
00034 #define VICVectAddr1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
00035 #define VICVectAddr2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
00036 #define VICVectAddr3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
00037 #define VICVectAddr4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
00038 #define VICVectAddr5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
00039 #define VICVectAddr6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
00040 #define VICVectAddr7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
00041 #define VICVectAddr8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
00042 #define VICVectAddr9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
00043 #define VICVectAddr10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
00044 #define VICVectAddr11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
00045 #define VICVectAddr12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
00046 #define VICVectAddr13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
00047 #define VICVectAddr14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
00048 #define VICVectAddr15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
00049 #define VICVectAddr16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140))
00050 #define VICVectAddr17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144))
00051 #define VICVectAddr18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148))
00052 #define VICVectAddr19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C))
00053 #define VICVectAddr20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150))
00054 #define VICVectAddr21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154))
00055 #define VICVectAddr22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158))
00056 #define VICVectAddr23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C))
00057 #define VICVectAddr24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160))
00058 #define VICVectAddr25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164))
00059 #define VICVectAddr26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168))
00060 #define VICVectAddr27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C))
00061 #define VICVectAddr28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170))
00062 #define VICVectAddr29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174))
00063 #define VICVectAddr30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178))
00064 #define VICVectAddr31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C))
00065 
00066 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
00067 these registers are known as "VICVectPriority(x)". */
00068 #define VICVectCntl0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00069 #define VICVectCntl1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00070 #define VICVectCntl2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00071 #define VICVectCntl3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00072 #define VICVectCntl4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00073 #define VICVectCntl5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00074 #define VICVectCntl6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00075 #define VICVectCntl7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00076 #define VICVectCntl8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00077 #define VICVectCntl9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00078 #define VICVectCntl10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00079 #define VICVectCntl11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00080 #define VICVectCntl12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00081 #define VICVectCntl13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00082 #define VICVectCntl14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00083 #define VICVectCntl15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00084 #define VICVectCntl16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
00085 #define VICVectCntl17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
00086 #define VICVectCntl18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
00087 #define VICVectCntl19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
00088 #define VICVectCntl20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
00089 #define VICVectCntl21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
00090 #define VICVectCntl22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
00091 #define VICVectCntl23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
00092 #define VICVectCntl24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
00093 #define VICVectCntl25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
00094 #define VICVectCntl26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
00095 #define VICVectCntl27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
00096 #define VICVectCntl28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
00097 #define VICVectCntl29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
00098 #define VICVectCntl30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
00099 #define VICVectCntl31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
00100 
00101 /* mthomas - added "real" names */
00102 #define VICVectPriority0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00103 #define VICVectPriority1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00104 #define VICVectPriority2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00105 #define VICVectPriority3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00106 #define VICVectPriority4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00107 #define VICVectPriority5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00108 #define VICVectPriority6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00109 #define VICVectPriority7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00110 #define VICVectPriority8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00111 #define VICVectPriority9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00112 #define VICVectPriority10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00113 #define VICVectPriority11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00114 #define VICVectPriority12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00115 #define VICVectPriority13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00116 #define VICVectPriority14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00117 #define VICVectPriority15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00118 #define VICVectPriority16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
00119 #define VICVectPriority17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
00120 #define VICVectPriority18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
00121 #define VICVectPriority19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
00122 #define VICVectPriority20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
00123 #define VICVectPriority21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
00124 #define VICVectPriority22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
00125 #define VICVectPriority23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
00126 #define VICVectPriority24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
00127 #define VICVectPriority25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
00128 #define VICVectPriority26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
00129 #define VICVectPriority27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
00130 #define VICVectPriority28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
00131 #define VICVectPriority29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
00132 #define VICVectPriority30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
00133 #define VICVectPriority31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
00134 
00135 
00136 #define VICVectAddr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00))
00137 
00138 
00139 /* Pin Connect Block */
00140 #define PINSEL_BASE_ADDR        0xE002C000
00141 #define PINSEL0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
00142 #define PINSEL1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
00143 #define PINSEL2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))
00144 #define PINSEL3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C))
00145 #define PINSEL4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10))
00146 #define PINSEL5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
00147 #define PINSEL6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18))
00148 #define PINSEL7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C))
00149 #define PINSEL8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20))
00150 #define PINSEL9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24))
00151 #define PINSEL10       (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28))
00152 
00153 #define PINMODE_BASE_ADDR       (PINSEL_BASE_ADDR+0x40)
00154 #define PINMODE0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40))
00155 #define PINMODE1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44))
00156 #define PINMODE2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48))
00157 #define PINMODE3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C))
00158 #define PINMODE4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50))
00159 #define PINMODE5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54))
00160 #define PINMODE6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58))
00161 #define PINMODE7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C))
00162 #define PINMODE8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60))
00163 #define PINMODE9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))
00164 
00165 /* General Purpose Input/Output (GPIO) */
00166 #define GPIO_BASE_ADDR          0xE0028000
00167 #define IOPIN0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
00168 #define IOSET0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
00169 #define IODIR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
00170 #define IOCLR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
00171 #define IOPIN1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
00172 #define IOSET1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
00173 #define IODIR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
00174 #define IOCLR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
00175 
00176 /* mthomas - alias */
00177 #define IO0PIN         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
00178 #define IO0SET         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
00179 #define IO0DIR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
00180 #define IO0CLR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
00181 #define IO1PIN         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
00182 #define IO1SET         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
00183 #define IO1DIR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
00184 #define IO1CLR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
00185 
00186 
00187 /* GPIO Interrupt Registers */
00188 #define IO0_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))
00189 #define IO0_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
00190 #define IO0_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))
00191 #define IO0_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))
00192 #define IO0_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))
00193 
00194 #define IO2_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0))
00195 #define IO2_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))
00196 #define IO2_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))
00197 #define IO2_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))
00198 #define IO2_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC))
00199 
00200 #define IO_INT_STAT     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
00201 
00202 #define PARTCFG_BASE_ADDR               0x3FFF8000
00203 #define PARTCFG        (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00))
00204 
00205 /* Fast I/O setup */
00206 #define FIO_BASE_ADDR           0x3FFFC000
00207 #define FIO0DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
00208 #define FIO0MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
00209 #define FIO0PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
00210 #define FIO0SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
00211 #define FIO0CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
00212 
00213 #define FIO1DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
00214 #define FIO1MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
00215 #define FIO1PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
00216 #define FIO1SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
00217 #define FIO1CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
00218 
00219 #define FIO2DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40))
00220 #define FIO2MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))
00221 #define FIO2PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))
00222 #define FIO2SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))
00223 #define FIO2CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))
00224 
00225 #define FIO3DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60))
00226 #define FIO3MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))
00227 #define FIO3PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))
00228 #define FIO3SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
00229 #define FIO3CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))
00230 
00231 #define FIO4DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80))
00232 #define FIO4MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))
00233 #define FIO4PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))
00234 #define FIO4SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))
00235 #define FIO4CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))
00236 
00237 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
00238 #define FIO0DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00))
00239 #define FIO1DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20))
00240 #define FIO2DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40))
00241 #define FIO3DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60))
00242 #define FIO4DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80))
00243 
00244 #define FIO0DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
00245 #define FIO1DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
00246 #define FIO2DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41))
00247 #define FIO3DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61))
00248 #define FIO4DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81))
00249 
00250 #define FIO0DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
00251 #define FIO1DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
00252 #define FIO2DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42))
00253 #define FIO3DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62))
00254 #define FIO4DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82))
00255 
00256 #define FIO0DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
00257 #define FIO1DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
00258 #define FIO2DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43))
00259 #define FIO3DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63))
00260 #define FIO4DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83))
00261 
00262 #define FIO0DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00))
00263 #define FIO1DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20))
00264 #define FIO2DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40))
00265 #define FIO3DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60))
00266 #define FIO4DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80))
00267 
00268 #define FIO0DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02))
00269 #define FIO1DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22))
00270 #define FIO2DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42))
00271 #define FIO3DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62))
00272 #define FIO4DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82))
00273 
00274 #define FIO0MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
00275 #define FIO1MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
00276 #define FIO2MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50))
00277 #define FIO3MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70))
00278 #define FIO4MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90))
00279 
00280 #define FIO0MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
00281 #define FIO1MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
00282 #define FIO2MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51))
00283 #define FIO3MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71))
00284 #define FIO4MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91))
00285 
00286 #define FIO0MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
00287 #define FIO1MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
00288 #define FIO2MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52))
00289 #define FIO3MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72))
00290 #define FIO4MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92))
00291 
00292 #define FIO0MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
00293 #define FIO1MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
00294 #define FIO2MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53))
00295 #define FIO3MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73))
00296 #define FIO4MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93))
00297 
00298 #define FIO0MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10))
00299 #define FIO1MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30))
00300 #define FIO2MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50))
00301 #define FIO3MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70))
00302 #define FIO4MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90))
00303 
00304 #define FIO0MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12))
00305 #define FIO1MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32))
00306 #define FIO2MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52))
00307 #define FIO3MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72))
00308 #define FIO4MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92))
00309 
00310 #define FIO0PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
00311 #define FIO1PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
00312 #define FIO2PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54))
00313 #define FIO3PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74))
00314 #define FIO4PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94))
00315 
00316 #define FIO0PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
00317 #define FIO1PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25))
00318 #define FIO2PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55))
00319 #define FIO3PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75))
00320 #define FIO4PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95))
00321 
00322 #define FIO0PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
00323 #define FIO1PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
00324 #define FIO2PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56))
00325 #define FIO3PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76))
00326 #define FIO4PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96))
00327 
00328 #define FIO0PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
00329 #define FIO1PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
00330 #define FIO2PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57))
00331 #define FIO3PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77))
00332 #define FIO4PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97))
00333 
00334 #define FIO0PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14))
00335 #define FIO1PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34))
00336 #define FIO2PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54))
00337 #define FIO3PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74))
00338 #define FIO4PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94))
00339 
00340 #define FIO0PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16))
00341 #define FIO1PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36))
00342 #define FIO2PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56))
00343 #define FIO3PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76))
00344 #define FIO4PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96))
00345 
00346 #define FIO0SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
00347 #define FIO1SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
00348 #define FIO2SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58))
00349 #define FIO3SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78))
00350 #define FIO4SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98))
00351 
00352 #define FIO0SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
00353 #define FIO1SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29))
00354 #define FIO2SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59))
00355 #define FIO3SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79))
00356 #define FIO4SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99))
00357 
00358 #define FIO0SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A))
00359 #define FIO1SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
00360 #define FIO2SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A))
00361 #define FIO3SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A))
00362 #define FIO4SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A))
00363 
00364 #define FIO0SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B))
00365 #define FIO1SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
00366 #define FIO2SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B))
00367 #define FIO3SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B))
00368 #define FIO4SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B))
00369 
00370 #define FIO0SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18))
00371 #define FIO1SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38))
00372 #define FIO2SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58))
00373 #define FIO3SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78))
00374 #define FIO4SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98))
00375 
00376 #define FIO0SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A))
00377 #define FIO1SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A))
00378 #define FIO2SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
00379 #define FIO3SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
00380 #define FIO4SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
00381 
00382 #define FIO0CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
00383 #define FIO1CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
00384 #define FIO2CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
00385 #define FIO3CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
00386 #define FIO4CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
00387 
00388 #define FIO0CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
00389 #define FIO1CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D))
00390 #define FIO2CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
00391 #define FIO3CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
00392 #define FIO4CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
00393 
00394 #define FIO0CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
00395 #define FIO1CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
00396 #define FIO2CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
00397 #define FIO3CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
00398 #define FIO4CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
00399 
00400 #define FIO0CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
00401 #define FIO1CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
00402 #define FIO2CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
00403 #define FIO3CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
00404 #define FIO4CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
00405 
00406 #define FIO0CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
00407 #define FIO1CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
00408 #define FIO2CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
00409 #define FIO3CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
00410 #define FIO4CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
00411 
00412 #define FIO0CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
00413 #define FIO1CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
00414 #define FIO2CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
00415 #define FIO3CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
00416 #define FIO4CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
00417 
00418 /* bit 0 in SCS register, port 0/1 are regular ports when bit 0 
00419 is 0,  fast ports when bit 0 is 1. */
00420 #define GPIOM         0x00000001
00421 
00422 /* System Control Block(SCB) modules include Memory Accelerator Module,
00423 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
00424 Reset, and Code Security/Debugging */
00425 #define SCB_BASE_ADDR   0xE01FC000
00426 
00427 /* Memory Accelerator Module (MAM) */
00428 #define MAMCR          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
00429 #define MAMTIM         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
00430 #define MEMMAP         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
00431 
00432 /* MEMMAP defines */
00433 #define MEMMAP_BBLK   0  /* Interrupt Vectors in Boot Block */
00434 #define MEMMAP_FLASH  1  /* Interrupt Vectors in Flash */
00435 #define MEMMAP_SRAM   2  /* Interrupt Vectors in SRAM */
00436 
00437 /* Phase Locked Loop (PLL) */
00438 #define PLLCON         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
00439 #define PLLCFG         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
00440 #define PLLSTAT        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
00441 #define PLLFEED        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
00442 
00443 /* Power Control */
00444 #define PCON           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
00445 #define PCONP          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
00446 
00447 /* Ackley: Added PCONP bit definitions */
00448                        /* bit 0 unused */
00449 #define PCTIM0         (1UL<<1)  /* Timer/counter 0 power/clock control bit */
00450 #define PCTIM1         (1UL<<2)  /* Timer/counter 1 power/clock control bit */
00451 #define PCUART0        (1UL<<3)  /* UART0 power/clock control bit */
00452 #define PCUART1        (1UL<<4)  /* UART1 power/clock control bit */
00453                        /* bit 5 unused */
00454 #define PCPWM1         (1UL<<6)  /* PWM1 power/clock control bit */
00455 #define PCI2C0         (1UL<<7)  /* I2C0 power/clock control bit */
00456 #define PCSPI          (1UL<<8)  /* SPI power/clock control bit */
00457 #define PCRTC          (1UL<<9)  /* RTC power/clock control bit */
00458 #define PCSSP1         (1UL<<10) /* SSP1 power/clock control bit */
00459 #define PCEMC          (1UL<<11) /* External Memory controller */
00460 #define PCAD           (1UL<<12) /* A/D converter power/clock control bit (needs special handling) */
00461 #define PCAN1          (1UL<<13) /* CAN Controller 1 power/clock control bit */
00462 #define PCAN2          (1UL<<14) /* CAN Controller 2 power/clock control bit */
00463                        /* bit 15 unused */
00464                        /* bit 16 unused */
00465                        /* bit 17 unused */
00466                        /* bit 18 unused */
00467 #define PCI2C1         (1UL<<19) /* I2C1 power/clock control bit */
00468                        /* bit 20 unused */
00469 #define PCSSP0         (1UL<<21) /* SSP0 power/clock control bit */
00470 #define PCTIM2         (1UL<<22) /* Timer 2 power/clock control bit */
00471 #define PCTIM3         (1UL<<23) /* Timer 3 power/clock control bit */
00472 #define PCUART2        (1UL<<24) /* UART2 power/clock control bit */
00473 #define PCUART3        (1UL<<25) /* UART3 power/clock control bit */
00474 #define PCI2C2         (1UL<<26) /* I2C2 power/clock control bit */
00475 #define PCI2S          (1UL<<27) /* I2S power/clock control bit */
00476 #define PCSDC          (1UL<<28) /* SD card power/clock control bit */
00477 #define PCGPDMA        (1UL<<29) /* GP DMA power/clock control bit */
00478 #define PCENET         (1UL<<30) /* Ethernet power/clock control bit */
00479 #define PCUSB          (1UL<<31) /* USB power/clock control bit */
00480 
00481 /* Clock Divider */
00482 /* #define APBDIV         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100)) */
00483 #define CCLKCFG        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
00484 #define USBCLKCFG      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
00485 #define CLKSRCSEL      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
00486 #define PCLKSEL0       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
00487 #define PCLKSEL1       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
00488 
00489 /* External Interrupts */
00490 #define EXTINT         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
00491 #define INTWAKE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
00492 #define EXTMODE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
00493 #define EXTPOLAR       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
00494 
00495 /* Reset, reset source identification */
00496 #define RSIR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
00497 
00498 /* RSID, code security protection */
00499 #define CSPR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
00500 
00501 /* AHB configuration */
00502 #define AHBCFG1        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
00503 #define AHBCFG2        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
00504 
00505 /* System Controls and Status */
00506 #define SCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
00507 
00508 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
00509 are for LPC24xx only. */
00510 #define STATIC_MEM0_BASE                0x80000000
00511 #define STATIC_MEM1_BASE                0x81000000
00512 #define STATIC_MEM2_BASE                0x82000000
00513 #define STATIC_MEM3_BASE                0x83000000
00514 
00515 #define DYNAMIC_MEM0_BASE               0xA0000000
00516 #define DYNAMIC_MEM1_BASE               0xB0000000
00517 #define DYNAMIC_MEM2_BASE               0xC0000000
00518 #define DYNAMIC_MEM3_BASE               0xD0000000
00519 
00520 /* External Memory Controller (EMC) */
00521 #define EMC_BASE_ADDR           0xFFE08000
00522 #define EMC_CTRL       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
00523 #define EMC_STAT       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
00524 #define EMC_CONFIG     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
00525 
00526 /* Dynamic RAM access registers */
00527 #define EMC_DYN_CTRL     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
00528 #define EMC_DYN_RFSH     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
00529 #define EMC_DYN_RD_CFG   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
00530 #define EMC_DYN_RP       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
00531 #define EMC_DYN_RAS      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
00532 #define EMC_DYN_SREX     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
00533 #define EMC_DYN_APR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
00534 #define EMC_DYN_DAL      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
00535 #define EMC_DYN_WR       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
00536 #define EMC_DYN_RC       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
00537 #define EMC_DYN_RFC      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
00538 #define EMC_DYN_XSR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
00539 #define EMC_DYN_RRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
00540 #define EMC_DYN_MRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
00541 
00542 #define EMC_DYN_CFG0     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
00543 #define EMC_DYN_RASCAS0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
00544 #define EMC_DYN_CFG1     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
00545 #define EMC_DYN_RASCAS1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
00546 #define EMC_DYN_CFG2     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
00547 #define EMC_DYN_RASCAS2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
00548 #define EMC_DYN_CFG3     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180))
00549 #define EMC_DYN_RASCAS3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184))
00550 
00551 /* static RAM access registers */
00552 #define EMC_STA_CFG0      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
00553 #define EMC_STA_WAITWEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
00554 #define EMC_STA_WAITOEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
00555 #define EMC_STA_WAITRD0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
00556 #define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
00557 #define EMC_STA_WAITWR0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
00558 #define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
00559 
00560 #define EMC_STA_CFG1      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
00561 #define EMC_STA_WAITWEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
00562 #define EMC_STA_WAITOEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
00563 #define EMC_STA_WAITRD1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
00564 #define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
00565 #define EMC_STA_WAITWR1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
00566 #define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
00567 
00568 #define EMC_STA_CFG2      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
00569 #define EMC_STA_WAITWEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
00570 #define EMC_STA_WAITOEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
00571 #define EMC_STA_WAITRD2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
00572 #define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
00573 #define EMC_STA_WAITWR2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
00574 #define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
00575 
00576 #define EMC_STA_CFG3      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
00577 #define EMC_STA_WAITWEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
00578 #define EMC_STA_WAITOEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
00579 #define EMC_STA_WAITRD3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
00580 #define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
00581 #define EMC_STA_WAITWR3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
00582 #define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
00583 
00584 #define EMC_STA_EXT_WAIT  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
00585 
00586 
00587 /* Timer 0 */
00588 #define TMR0_BASE_ADDR          0xE0004000
00589 #define T0IR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
00590 #define T0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
00591 #define T0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
00592 #define T0PR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
00593 #define T0PC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
00594 #define T0MCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
00595 #define T0MR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
00596 #define T0MR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
00597 #define T0MR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
00598 #define T0MR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
00599 #define T0CCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
00600 #define T0CR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
00601 #define T0CR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
00602 #define T0CR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
00603 #define T0CR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
00604 #define T0EMR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
00605 #define T0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
00606 
00607 /* Timer 1 */
00608 #define TMR1_BASE_ADDR          0xE0008000
00609 #define T1IR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
00610 #define T1TCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
00611 #define T1TC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
00612 #define T1PR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
00613 #define T1PC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
00614 #define T1MCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
00615 #define T1MR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
00616 #define T1MR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
00617 #define T1MR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
00618 #define T1MR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
00619 #define T1CCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
00620 #define T1CR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
00621 #define T1CR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
00622 #define T1CR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
00623 #define T1CR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
00624 #define T1EMR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
00625 #define T1CTCR         (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
00626 
00627 /* Timer 2 */
00628 #define TMR2_BASE_ADDR          0xE0070000
00629 #define T2IR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
00630 #define T2TCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
00631 #define T2TC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
00632 #define T2PR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
00633 #define T2PC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
00634 #define T2MCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
00635 #define T2MR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
00636 #define T2MR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
00637 #define T2MR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
00638 #define T2MR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
00639 #define T2CCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
00640 #define T2CR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
00641 #define T2CR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
00642 #define T2CR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
00643 #define T2CR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
00644 #define T2EMR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
00645 #define T2CTCR         (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
00646 
00647 /* Timer 3 */
00648 #define TMR3_BASE_ADDR          0xE0074000
00649 #define T3IR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
00650 #define T3TCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
00651 #define T3TC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
00652 #define T3PR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
00653 #define T3PC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
00654 #define T3MCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
00655 #define T3MR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
00656 #define T3MR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
00657 #define T3MR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
00658 #define T3MR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
00659 #define T3CCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
00660 #define T3CR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
00661 #define T3CR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
00662 #define T3CR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
00663 #define T3CR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
00664 #define T3EMR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
00665 #define T3CTCR         (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
00666 
00667 /* Pulse Width Modulator (PWM) */
00668 #define PWM0_BASE_ADDR          0xE0014000
00669 #define PWM0IR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
00670 #define PWM0TCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
00671 #define PWM0TC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
00672 #define PWM0PR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C))
00673 #define PWM0PC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10))
00674 #define PWM0MCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14))
00675 #define PWM0MR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18))
00676 #define PWM0MR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C))
00677 #define PWM0MR2         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20))
00678 #define PWM0MR3         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24))
00679 #define PWM0CCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28))
00680 #define PWM0CR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C))
00681 #define PWM0CR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30))
00682 #define PWM0CR2         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34))
00683 #define PWM0CR3         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38))
00684 #define PWM0EMR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C))
00685 #define PWM0MR4         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40))
00686 #define PWM0MR5         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44))
00687 #define PWM0MR6         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48))
00688 #define PWM0PCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C))
00689 #define PWM0LER         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
00690 #define PWM0CTCR        (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))
00691 
00692 #define PWM1_BASE_ADDR          0xE0018000
00693 #define PWM1IR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
00694 #define PWM1TCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
00695 #define PWM1TC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
00696 #define PWM1PR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
00697 #define PWM1PC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
00698 #define PWM1MCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
00699 #define PWM1MR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
00700 #define PWM1MR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
00701 #define PWM1MR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
00702 #define PWM1MR3         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
00703 #define PWM1CCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
00704 #define PWM1CR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
00705 #define PWM1CR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
00706 #define PWM1CR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))
00707 #define PWM1CR3         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))
00708 #define PWM1EMR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C))
00709 #define PWM1MR4         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))
00710 #define PWM1MR5         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))
00711 #define PWM1MR6         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))
00712 #define PWM1PCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))
00713 #define PWM1LER         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))
00714 #define PWM1CTCR        (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))
00715 
00716 /* Ackley: Added Generic UART offsets */
00717 #define UxRBR          0x00
00718 #define UxTHR          0x00
00719 #define UxDLL          0x00
00720 #define UxDLM          0x04
00721 #define UxIER          0x04
00722 #define UxIIR          0x08
00723 #define UxFCR          0x08
00724 #define UxLCR          0x0C
00725 #define UxLSR          0x14
00726 #define UxSCR          0x1C
00727 #define UxACR          0x20
00728 #define UxICR          0x24
00729 #define UxFDR          0x28
00730 #define UxTER          0x30
00731 
00732 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
00733 #define UART0_BASE_ADDR         0xE000C000
00734 #define U0RBR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00735 #define U0THR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00736 #define U0DLL          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00737 #define U0DLM          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00738 #define U0IER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00739 #define U0IIR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00740 #define U0FCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00741 #define U0LCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
00742 #define U0LSR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
00743 #define U0SCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
00744 #define U0ACR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
00745 #define U0ICR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24))
00746 #define U0FDR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
00747 #define U0TER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
00748 
00749 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
00750 #define UART1_BASE_ADDR         0xE0010000
00751 #define U1RBR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00752 #define U1THR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00753 #define U1DLL          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00754 #define U1DLM          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00755 #define U1IER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00756 #define U1IIR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00757 #define U1FCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00758 #define U1LCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
00759 #define U1MCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
00760 #define U1LSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
00761 #define U1MSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
00762 #define U1SCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
00763 #define U1ACR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
00764 /*#define U1ICR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x24)) ACKLEY -- Only this one was missing from the file, why? */
00765 #define U1FDR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
00766 #define U1TER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
00767 
00768 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
00769 #define UART2_BASE_ADDR         0xE0078000
00770 #define U2RBR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00771 #define U2THR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00772 #define U2DLL          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00773 #define U2DLM          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
00774 #define U2IER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
00775 #define U2IIR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
00776 #define U2FCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
00777 #define U2LCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
00778 #define U2LSR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
00779 #define U2SCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
00780 #define U2ACR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
00781 #define U2ICR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24))
00782 #define U2FDR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
00783 #define U2TER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
00784 
00785 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
00786 #define UART3_BASE_ADDR         0xE007C000
00787 #define U3RBR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00788 #define U3THR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00789 #define U3DLL          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00790 #define U3DLM          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
00791 #define U3IER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
00792 #define U3IIR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
00793 #define U3FCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
00794 #define U3LCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
00795 #define U3LSR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
00796 #define U3SCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
00797 #define U3ACR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
00798 #define U3ICR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
00799 #define U3FDR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
00800 #define U3TER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
00801 
00802 /* I2C Interface 0 */
00803 #define I2C0_BASE_ADDR          0xE001C000
00804 #define I20CONSET      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
00805 #define I20STAT        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
00806 #define I20DAT         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
00807 #define I20ADR         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
00808 #define I20SCLH        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
00809 #define I20SCLL        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
00810 #define I20CONCLR      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
00811 
00812 /* I2C Interface 1 */
00813 #define I2C1_BASE_ADDR          0xE005C000
00814 #define I21CONSET      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
00815 #define I21STAT        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
00816 #define I21DAT         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
00817 #define I21ADR         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
00818 #define I21SCLH        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
00819 #define I21SCLL        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
00820 #define I21CONCLR      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
00821 
00822 /* I2C Interface 2 */
00823 #define I2C2_BASE_ADDR          0xE0080000
00824 #define I22CONSET      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
00825 #define I22STAT        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
00826 #define I22DAT         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
00827 #define I22ADR         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
00828 #define I22SCLH        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
00829 #define I22SCLL        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
00830 #define I22CONCLR      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
00831 
00832 /* SPI0 (Serial Peripheral Interface 0) */
00833 #define SPI0_BASE_ADDR          0xE0020000
00834 #define S0SPCR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
00835 #define S0SPSR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
00836 #define S0SPDR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
00837 #define S0SPCCR        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
00838 #define S0SPINT        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
00839 
00840 /* SSP0 Controller */
00841 #define SSP0_BASE_ADDR          0xE0068000
00842 #define SSP0CR0        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
00843 #define SSP0CR1        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
00844 #define SSP0DR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
00845 #define SSP0SR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
00846 #define SSP0CPSR       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
00847 #define SSP0IMSC       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
00848 #define SSP0RIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
00849 #define SSP0MIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
00850 #define SSP0ICR        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
00851 #define SSP0DMACR      (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
00852 
00853 /* SSP1 Controller */
00854 #define SSP1_BASE_ADDR          0xE0030000
00855 #define SSP1CR0        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
00856 #define SSP1CR1        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
00857 #define SSP1DR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
00858 #define SSP1SR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
00859 #define SSP1CPSR       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
00860 #define SSP1IMSC       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
00861 #define SSP1RIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
00862 #define SSP1MIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
00863 #define SSP1ICR        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
00864 #define SSP1DMACR      (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
00865 
00866 
00867 /* Real Time Clock */
00868 #define RTC_BASE_ADDR           0xE0024000
00869 #define RTC_ILR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
00870 #define RTC_CTC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
00871 #define RTC_CCR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
00872 #define RTC_CIIR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
00873 #define RTC_AMR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
00874 #define RTC_CTIME0      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
00875 #define RTC_CTIME1      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
00876 #define RTC_CTIME2      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
00877 #define RTC_SEC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
00878 #define RTC_MIN         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
00879 #define RTC_HOUR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
00880 #define RTC_DOM         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
00881 #define RTC_DOW         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
00882 #define RTC_DOY         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
00883 #define RTC_MONTH       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
00884 #define RTC_YEAR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
00885 #define RTC_CISS        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
00886 #define RTC_ALSEC       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
00887 #define RTC_ALMIN       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
00888 #define RTC_ALHOUR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
00889 #define RTC_ALDOM       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
00890 #define RTC_ALDOW       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
00891 #define RTC_ALDOY       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
00892 #define RTC_ALMON       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
00893 #define RTC_ALYEAR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
00894 #define RTC_PREINT      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
00895 #define RTC_PREFRAC     (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
00896 
00897 
00898 /* A/D Converter 0 (AD0) */
00899 #define AD0_BASE_ADDR           0xE0034000
00900 #define AD0CR          (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
00901 #define AD0GDR         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
00902 #define AD0INTEN       (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
00903 #define AD0DR0         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
00904 #define AD0DR1         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
00905 #define AD0DR2         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
00906 #define AD0DR3         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
00907 #define AD0DR4         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
00908 #define AD0DR5         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
00909 #define AD0DR6         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
00910 #define AD0DR7         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
00911 #define AD0STAT        (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
00912 
00913 
00914 /* D/A Converter */
00915 #define DAC_BASE_ADDR           0xE006C000
00916 #define DACR           (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
00917 
00918 
00919 /* Watchdog */
00920 #define WDG_BASE_ADDR           0xE0000000
00921 #define WDMOD          (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
00922 #define WDTC           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
00923 #define WDFEED         (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
00924 #define WDTV           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
00925 #define WDCLKSEL       (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
00926 
00927 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
00928 #define CAN_ACCEPT_BASE_ADDR            0xE003C000
00929 #define CAN_AFMR                (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))
00930 #define CAN_SFF_SA              (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))
00931 #define CAN_SFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
00932 #define CAN_EFF_SA              (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
00933 #define CAN_EFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
00934 #define CAN_EOT                 (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
00935 #define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
00936 #define CAN_LUT_ERR     (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
00937 
00938 #define CAN_CENTRAL_BASE_ADDR           0xE0040000
00939 #define CAN_TX_SR       (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
00940 #define CAN_RX_SR       (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
00941 #define CAN_MSR         (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
00942 
00943 #define CAN1_BASE_ADDR          0xE0044000
00944 #define CAN1MOD         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
00945 #define CAN1CMR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
00946 #define CAN1GSR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
00947 #define CAN1ICR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
00948 #define CAN1IER         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
00949 #define CAN1BTR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
00950 #define CAN1EWL         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
00951 #define CAN1SR          (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
00952 #define CAN1RFS         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
00953 #define CAN1RID         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
00954 #define CAN1RDA         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
00955 #define CAN1RDB         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
00956 
00957 #define CAN1TFI1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
00958 #define CAN1TID1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
00959 #define CAN1TDA1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
00960 #define CAN1TDB1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
00961 #define CAN1TFI2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
00962 #define CAN1TID2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
00963 #define CAN1TDA2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
00964 #define CAN1TDB2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
00965 #define CAN1TFI3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
00966 #define CAN1TID3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
00967 #define CAN1TDA3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
00968 #define CAN1TDB3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
00969 
00970 #define CAN2_BASE_ADDR          0xE0048000
00971 #define CAN2MOD         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
00972 #define CAN2CMR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
00973 #define CAN2GSR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
00974 #define CAN2ICR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
00975 #define CAN2IER         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
00976 #define CAN2BTR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
00977 #define CAN2EWL         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
00978 #define CAN2SR          (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
00979 #define CAN2RFS         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
00980 #define CAN2RID         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
00981 #define CAN2RDA         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
00982 #define CAN2RDB         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
00983 
00984 #define CAN2TFI1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
00985 #define CAN2TID1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
00986 #define CAN2TDA1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
00987 #define CAN2TDB1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
00988 #define CAN2TFI2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
00989 #define CAN2TID2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
00990 #define CAN2TDA2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
00991 #define CAN2TDB2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
00992 #define CAN2TFI3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
00993 #define CAN2TID3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
00994 #define CAN2TDA3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
00995 #define CAN2TDB3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
00996 
00997 
00998 /* MultiMedia Card Interface(MCI) Controller */
00999 #define MCI_BASE_ADDR           0xE008C000
01000 #define MCI_POWER      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
01001 #define MCI_CLOCK      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
01002 #define MCI_ARGUMENT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
01003 #define MCI_COMMAND    (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C))
01004 #define MCI_RESP_CMD   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10))
01005 #define MCI_RESP0      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14))
01006 #define MCI_RESP1      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18))
01007 #define MCI_RESP2      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C))
01008 #define MCI_RESP3      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20))
01009 #define MCI_DATA_TMR   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24))
01010 #define MCI_DATA_LEN   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28))
01011 #define MCI_DATA_CTRL  (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C))
01012 #define MCI_DATA_CNT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30))
01013 #define MCI_STATUS     (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34))
01014 #define MCI_CLEAR      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38))
01015 #define MCI_MASK0      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C))
01016 #define MCI_MASK1      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40))
01017 #define MCI_FIFO_CNT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48))
01018 #define MCI_FIFO       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80))
01019 
01020 
01021 /* I2S Interface Controller (I2S) */
01022 #define I2S_BASE_ADDR           0xE0088000
01023 #define I2S_DAO        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
01024 #define I2S_DAI        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
01025 #define I2S_TX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
01026 #define I2S_RX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
01027 #define I2S_STATE      (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
01028 #define I2S_DMA1       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
01029 #define I2S_DMA2       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
01030 #define I2S_IRQ        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
01031 #define I2S_TXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
01032 #define I2S_RXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
01033 
01034 
01035 /* General-purpose DMA Controller */
01036 #define DMA_BASE_ADDR           0xFFE04000
01037 #define GPDMA_INT_STAT         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
01038 #define GPDMA_INT_TCSTAT       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
01039 #define GPDMA_INT_TCCLR        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
01040 #define GPDMA_INT_ERR_STAT     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
01041 #define GPDMA_INT_ERR_CLR      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
01042 #define GPDMA_RAW_INT_TCSTAT   (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
01043 #define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
01044 #define GPDMA_ENABLED_CHNS     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
01045 #define GPDMA_SOFT_BREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
01046 #define GPDMA_SOFT_SREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
01047 #define GPDMA_SOFT_LBREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
01048 #define GPDMA_SOFT_LSREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
01049 #define GPDMA_CONFIG           (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
01050 #define GPDMA_SYNC             (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
01051 
01052 /* DMA channel 0 registers */
01053 #define GPDMA_CH0_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
01054 #define GPDMA_CH0_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
01055 #define GPDMA_CH0_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
01056 #define GPDMA_CH0_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
01057 #define GPDMA_CH0_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
01058 
01059 /* DMA channel 1 registers */
01060 #define GPDMA_CH1_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
01061 #define GPDMA_CH1_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
01062 #define GPDMA_CH1_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
01063 #define GPDMA_CH1_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
01064 #define GPDMA_CH1_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
01065 
01066 
01067 /* USB Controller */
01068 #define USB_INT_BASE_ADDR       0xE01FC1C0
01069 #define USB_BASE_ADDR           0xFFE0C200              /* USB Base Address */
01070 
01071 #define USB_INT_STAT    (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
01072 
01073 /* USB Device Interrupt Registers */
01074 #define DEV_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
01075 #define DEV_INT_EN      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
01076 #define DEV_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
01077 #define DEV_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
01078 #define DEV_INT_PRIO    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
01079 
01080 /* USB Device Endpoint Interrupt Registers */
01081 #define EP_INT_STAT     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
01082 #define EP_INT_EN       (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
01083 #define EP_INT_CLR      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
01084 #define EP_INT_SET      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
01085 #define EP_INT_PRIO     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
01086 
01087 /* USB Device Endpoint Realization Registers */
01088 #define REALIZE_EP      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
01089 #define EP_INDEX        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
01090 #define MAXPACKET_SIZE  (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
01091 
01092 /* USB Device Command Reagisters */
01093 #define CMD_CODE        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
01094 #define CMD_DATA        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
01095 
01096 /* USB Device Data Transfer Registers */
01097 #define RX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
01098 #define TX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
01099 #define RX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
01100 #define TX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
01101 #define USB_CTRL        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
01102 
01103 /* USB Device DMA Registers */
01104 #define DMA_REQ_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
01105 #define DMA_REQ_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
01106 #define DMA_REQ_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
01107 #define UDCA_HEAD           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
01108 #define EP_DMA_STAT         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
01109 #define EP_DMA_EN           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
01110 #define EP_DMA_DIS          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
01111 #define DMA_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
01112 #define DMA_INT_EN          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
01113 #define EOT_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
01114 #define EOT_INT_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
01115 #define EOT_INT_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
01116 #define NDD_REQ_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
01117 #define NDD_REQ_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
01118 #define NDD_REQ_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
01119 #define SYS_ERR_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
01120 #define SYS_ERR_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
01121 #define SYS_ERR_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))
01122 
01123 /* USB Host and OTG registers are for LPC24xx only */
01124 /* USB Host Controller */
01125 #define USBHC_BASE_ADDR         0xFFE0C000
01126 #define HC_REVISION         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
01127 #define HC_CONTROL          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
01128 #define HC_CMD_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
01129 #define HC_INT_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))
01130 #define HC_INT_EN           (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))
01131 #define HC_INT_DIS          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))
01132 #define HC_HCCA             (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))
01133 #define HC_PERIOD_CUR_ED    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))
01134 #define HC_CTRL_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))
01135 #define HC_CTRL_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))
01136 #define HC_BULK_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28))
01137 #define HC_BULK_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C))
01138 #define HC_DONE_HEAD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30))
01139 #define HC_FM_INTERVAL      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34))
01140 #define HC_FM_REMAINING     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38))
01141 #define HC_FM_NUMBER        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C))
01142 #define HC_PERIOD_START     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40))
01143 #define HC_LS_THRHLD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44))
01144 #define HC_RH_DESCA         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48))
01145 #define HC_RH_DESCB         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C))
01146 #define HC_RH_STAT          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50))
01147 #define HC_RH_PORT_STAT1    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54))
01148 #define HC_RH_PORT_STAT2    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))
01149 
01150 /* USB OTG Controller */
01151 #define USBOTG_BASE_ADDR        0xFFE0C100
01152 #define OTG_INT_STAT        (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))
01153 #define OTG_INT_EN          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))
01154 #define OTG_INT_SET         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))
01155 #define OTG_INT_CLR         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))
01156 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
01157 #define OTG_STAT_CTRL       (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
01158 #define OTG_TIMER           (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))
01159 
01160 #define USBOTG_I2C_BASE_ADDR    0xFFE0C300
01161 #define OTG_I2C_RX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
01162 #define OTG_I2C_TX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
01163 #define OTG_I2C_STS         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))
01164 #define OTG_I2C_CTL         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08))
01165 #define OTG_I2C_CLKHI       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))
01166 #define OTG_I2C_CLKLO       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))
01167 
01168 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
01169 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
01170 #define USBOTG_CLK_BASE_ADDR    0xFFE0CFF0
01171 #define OTG_CLK_CTRL        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
01172 #define OTG_CLK_STAT        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
01173 
01174 /* Note: below three register name convention is for LPC23xx USB device only, match
01175 with the spec. update in USB Device Section. */
01176 #define USBPortSel          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
01177 #define USBClkCtrl          (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
01178 #define USBClkSt            (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
01179 
01180 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
01181 #define MAC_BASE_ADDR           0xFFE00000 /* AHB Peripheral # 0 */
01182 #define MAC_MAC1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
01183 #define MAC_MAC2            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
01184 #define MAC_IPGT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
01185 #define MAC_IPGR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
01186 #define MAC_CLRT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
01187 #define MAC_MAXF            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
01188 #define MAC_SUPP            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
01189 #define MAC_TEST            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
01190 #define MAC_MCFG            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
01191 #define MAC_MCMD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
01192 #define MAC_MADR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
01193 #define MAC_MWTD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
01194 #define MAC_MRDD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
01195 #define MAC_MIND            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
01196 
01197 #define MAC_SA0             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
01198 #define MAC_SA1             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
01199 #define MAC_SA2             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
01200 
01201 #define MAC_COMMAND         (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
01202 #define MAC_STATUS          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
01203 #define MAC_RXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
01204 #define MAC_RXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
01205 #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
01206 #define MAC_RXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
01207 #define MAC_RXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
01208 #define MAC_TXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
01209 #define MAC_TXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
01210 #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
01211 #define MAC_TXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
01212 #define MAC_TXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
01213 
01214 #define MAC_TSV0            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
01215 #define MAC_TSV1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
01216 #define MAC_RSV             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
01217 
01218 #define MAC_FLOWCONTROLCNT  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
01219 #define MAC_FLOWCONTROLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
01220 
01221 #define MAC_RXFILTERCTRL    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
01222 #define MAC_RXFILTERWOLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
01223 #define MAC_RXFILTERWOLCLR  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
01224 
01225 #define MAC_HASHFILTERL     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
01226 #define MAC_HASHFILTERH     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
01227 
01228 #define MAC_INTSTATUS       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
01229 #define MAC_INTENABLE       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
01230 #define MAC_INTCLEAR        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
01231 #define MAC_INTSET          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
01232 
01233 #define MAC_POWERDOWN       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
01234 #define MAC_MODULEID        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
01235 
01236 
01237 /* Some bit-mask definitions - mthomas */
01238 
01239 /* Timers */
01240 #define TxIR_MR0_Interrupt (1UL<<0)
01241 #define TxIR_MR1_Interrupt (1UL<<1)
01242 #define TxIR_MR2_Interrupt (1UL<<2)
01243 #define TxIR_MR3_Interrupt (1UL<<3)
01244 #define TxIR_CR0_Interrupt (1UL<<4)
01245 #define TxIR_CR1_Interrupt (1UL<<5)
01246 #define TxIR_CR2_Interrupt (1UL<<6)
01247 #define TxIR_CR3_Interrupt (1UL<<7)
01248 
01249 #define TxTCR_Counter_Enable (1UL<<0)
01250 #define TxTCR_Counter_Reset  (1UL<<1)
01251 
01252 #define TxMCR_MR0I  (1UL<<0)
01253 #define TxMCR_MR0R  (1UL<<1)
01254 #define TxMCR_MR0S  (1UL<<2)
01255 #define TxMCR_MR1I  (1UL<<3)
01256 #define TxMCR_MR1R  (1UL<<4)
01257 #define TxMCR_MR1S  (1UL<<5)
01258 #define TxMCR_MR2I  (1UL<<6)
01259 #define TxMCR_MR2R  (1UL<<7)
01260 #define TxMCR_MR2S  (1UL<<8)
01261 #define TxMCR_MR3I  (1UL<<9)
01262 #define TxMCR_MR3R  (1UL<<10)
01263 #define TxMCR_MR3S  (1UL<<11)
01264 
01265 /* VIC */
01266 #define VIC_CHAN_NUM_WDT      0
01267 #define VIC_CHAN_NUM_UNUSED   1
01268 #define VIC_CHAN_NUM_ARM_Core_DgbCommRX 2
01269 #define VIC_CHAN_NUM_ARM_Core_DbgCommTX 3
01270 #define VIC_CHAN_NUM_Timer0   4
01271 #define VIC_CHAN_NUM_Timer1   5
01272 #define VIC_CHAN_NUM_UART0    6
01273 #define VIC_CHAN_NUM_UART1    7
01274 #define VIC_CHAN_NUM_PWM1     8
01275 #define VIC_CHAN_NUM_I2C0     9
01276 #define VIC_CHAN_NUM_SPI     10
01277 #define VIC_CHAN_NUM_SSP0    10
01278 #define VIC_CHAN_NUM_SSP1    11
01279 #define VIC_CHAN_NUM_PLL     12
01280 #define VIC_CHAN_NUM_RTC     13
01281 #define VIC_CHAN_NUM_EINT0   14
01282 #define VIC_CHAN_NUM_EINT1   15
01283 #define VIC_CHAN_NUM_EINT2   16
01284 #define VIC_CHAN_NUM_EINT3   17
01285 #define VIC_CHAN_NUM_ADC0    18
01286 #define VIC_CHAN_NUM_I2C1    19
01287 #define VIC_CHAN_NUM_BOD     20
01288 #define VIC_CHAN_NUM_Ethernet 21
01289 #define VIC_CHAN_NUM_USB     22
01290 #define VIC_CHAN_NUM_CAN     23
01291 #define VIC_CHAN_NUM_SD_MMC  24
01292 #define VIC_CHAN_NUM_GP_DMA  25
01293 #define VIC_CHAN_NUM_Timer2  26
01294 #define VIC_CHAN_NUM_Timer3  27
01295 #define VIC_CHAN_NUM_UART2   28
01296 #define VIC_CHAN_NUM_UART3   29
01297 #define VIC_CHAN_NUM_I2C2    30
01298 #define VIC_CHAN_NUM_I2S     31
01299 
01300 #define VIC_CHAN_TO_MASK(vctm_chan_num__) (1UL<<vctm_chan_num__)
01301 
01302 #endif  /* __LPC23xx_H */
01303